Resistive Random Access Memory (RRAM) as a newly-emerging non-volatile storage technology has great advantages compared with FLASH in various aspects, such as cell area, device density, power consumption, programming/erasing speed, 3D (three-dimensional) integration, and multi-value implementation, and therefore draws much attention of both domestic and abroad companies as well as research institutions. With a continuous development, the resistive random memory has become one of the most competent candidates for mainstream products of the future non-volatile memory.
The resistive random memory has a simple memory cell structure of electrode/insulating layer/electrode. As a result, an 1R intersection array structure is a very ideal storage array structure, which enables 3D integration with a very high density. In the intersection array structure, memory cells are arranged at parallel intersectional points which are aligned in a vertical direction, wherein each memory cell can be selected and accessed. However, due to symmetrical electrical characteristics of the memory cells, the 1R intersection array structure has a serious read crosstalk problem.
FIG. 1 is a schematic view showing the read crosstalk problem in a resistive random memory in the prior art. As shown in FIG. 1, each memory comprises an upper electrode, a resistive layer, and a lower electrode. The process for manufacturing the array structure is simple, and the array structure is easy to be three-dimensionally integrated at low cost and with a high density. However, the structure has an obvious read crosstalk problem. FIG. 1 shows four adjacent memory cells, wherein a memory cell at a position (1, 1) is at a high-resistance state, while the other three memory cells at positions (1, 2), (2, 2), and (2, 1) are all at a low-resistance state. A solid line in FIG. 1 shows a desired current path when a read voltage is applied on the memory cell at the position (1, 1). In contrast, a spotted line in FIG. 1 shows an actual current path, as a result of which a resistance value being read out is not the resistance value of the memory cell at the position (1, 1). This is an example of the read crosstalk problem.
The read crosstalk problem is typically solved by means of a selection unit, as in an 1T1R structure or an 1D1R structure. The cell area in an integration scheme using the 1T1R structure is determined by transistors. A smallest area of a resistive random memory cell having the 1T1R structure is 6F2, if influence of driving current of the transistors is not taken into consideration, wherein F is a feature line-width. As a result, the 1T1R structure cannot be used in high-density array integration, while the 1D1R structure is considered to be more competent for application.
FIG. 2 is a schematic view of a resistive random memory having the 1D1R structure of the prior art. As shown in FIG. 2, in a resistive random memory cell, the read cross problem can be effectively solved by connecting a rectifying diode with a resistive layer in serial. The rectifying diode is implemented by a PN junction. The resistive layer is typically formed of a metal material. The process for manufacturing the 1D1R cell comprising the PN junction rectifying diode comprises n-type doping and p-type doping processes in formation of the PN junctions, and a subsequent high-temperature activation process. As a result, 3D integration of the 1D1R cells (shown in FIG. 2) is very complex and difficult to control. The PN junction typically has a thickness of more than 100 nm, which also constitute an obstacle to the 3D integration. Furthermore, a polysilicon PN junction diode can provide high Set/Reset current required by the resistive random memory cell, but it has large leakage current. These factors are all disadvantageous to the integration of the resistive random memory cells utilizing the typical polysilicon PN junction rectifying devices. Therefore, implementation of the 3D high-density integration of the resistive random memory cells having the 1D1R structure has become an important topic of memory technology.
The inventor has noticed that the prior art has a problem that in the resistive random memory cell having the 1D1R structure, which utilizes the PN junction as the selection unit, the 3D high-density integration is difficult due to the doping process and the high-temperature activation process.